As is well known in the field of analog signal processing, four-quadrant analog multiplier circuits are fundamental building blocks for many circuit applications. These circuit applications include phase detectors in phase-locked loops (PLLs), frequency translators, AM modulator circuits, RF mixer circuits, and receiver circuitry of the heterodyne, super heterodyne, and homodyne type. These circuits are particularly useful in applications such as audio and video signal processing, transmission and receipt of analog signals, and adaptive filters such as correlators and convolution circuits.
As is also known in the art, the term "four-quadrant" multiplier refers to a circuit for multiplying two signed analog signals. Conventional four-quadrant multiplier circuits include those circuits which depend upon variations in transconductance in differential stages, and those circuits which are hardware implementations of a quadratic algebraic function (and rely upon the quadratic characteristics of MOS transistors).
The most widely-used analog multiplier circuit is commonly referred to as the "Gilbert Cell", described in Gilbert "A precise Four-Quadrant Multiplier with Subnanosecond Response", J. Sol. State Circ., Vol. SC-3 (IEEE, December 1968), pp. 365-373; Gilbert, "A Four-Quadrant Analog Divider/Multiplier with 0.01% Distortion", Digest of Technical Papers: 1983 Int'l Sol. State Circ. Conf. (IEEE, 1983), pp. 248-249; and in Gray and Meyer, Analysis and Design of Analog Integrated Circuits, (John Wiley & Sons, 1977), pp. 563-570. The Gilbert Cell, which is realized using bipolar transistors, relies upon variations in transconductance of three differential stages to perform the multiplication. While the Gilbert Cell generally provides high frequency performance, the input dynamic range is limited by the bipolar realization. Furthermore, the active power dissipation of the bipolar Gilbert Cell circuit is quite high, being on the order of 50 mW or greater, depending upon the frequency band, upon the dynamic input signal range, and upon whether prestage circuitry is provided. In addition, the power supply voltage required for conventional bipolar Gilbert Cell realizations is also quite high, generally being on the order of 5 volts when implemented with modern technology.
MOS and complementary-MOS (CMOS) realizations of Gilbert Cell multipliers are also known in the art. MOS technology offers the benefit of reduced power dissipation and reduced manufacturing cost. Examples of such implementations may be found in Babanezhad, et al., "A 20 V Four-Quadrant CMOS Analog Multiplier", J. Sol. State Circ., Vol. SC-20, No. 6 (IEEE, 1985); Wang, "A CMOS Four-Quadrant Analog Multiplier with Single-Ended Voltage Output and Improved Temperature Performances", J. Sol. State Circ., Vol. SC-26, No. 9 (IEEE, 1991); Qin, et al., "A .+-.5 V CMOS Analog Multiplier", J. Sol. State Circ., Vol. SC-22, No. 6 (IEEE, 1987); and Wong, et al., "Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Linearized Transconductance Stages", J. Sol. State Circ., Vol. SC-21, No. 6 (IEEE, 1986). It is believed, however, that conventional MOS or CMOS Gilbert Cell multipliers tend to exhibit poor linearity for a given supply voltage, and as such are not well-suited for the important low voltage applications now increasing in popularity, particularly in the telecommunications and portable computing system fields.
Analog multipliers that rely upon the square-law MOS transistor characteristics have been reported to have improved linearity over the Gilbert Cell multipliers discussed above. Attention is directed to "An MOS Four-Quadrant Analog Multiplier Using Simple Two-Input Squaring Circuits with Source Followers", J. Sol. State Circ., Vol. SC-25, No. 3 (IEEE, 1990); Pena-Finol, et al., "A MOS Four-Quadrant Analog Multiplier Using the Quarter-Square Technique", J. Sol. State Circ., Vol. SC-22, No. 6 (IEEE, 1987); and Kim, et al., "Four-Quadrant CMOS Analogue Multiplier", Electronic Letters, Vol. 22, No. 7 (March 1992). As is known in the art, analog multipliers of these types tend to be quite complex, requiring a large number of transistors. For example, the Kim et al. paper describes a multiplier which uses two buffers in a feedback arrangement, with two differential stages and a current mirror. This complexity also tends to limit the bandwidth of these circuits.
By way of further background, U.S. Pat. No. 5,332,937 issued Jul. 26, 1994, assigned to SGS-Thomson Microelectronics, S.r.l., and incorporated herein by this reference, describes a BiCMOS transconductance stage as used in high-frequency continuous-time filters. In this transconductor, cascode-connected bipolar transistors maintain a relatively constant drain-to-source voltage for MOS transistors that receive a differential input at their gates. These MOS transistors remain biased in the triode, or linear, region. This arrangement allows generation of an output differential current that is quite linear to the differential input voltage, and with excellent high frequency performance.
Referring to FIG. 1, transconductance stage 10 constructed according to the above-incorporated U.S. Pat. No. 5,332,937, will be described in detail. Transconductance stage 10 includes two differential legs that conduct currents I.sub.0+ and I.sub.0-, respectively, and a reference leg that conducts current I.sub.D. One differential leg includes bipolar transistor 12a and MOS transistor 14a, connected in series (i.e., with the drain of transistor 14a connected to the emitter of transistor 12a); the gate of MOS transistor 14a receives input voltage V.sub.i+. Similarly, the second differential leg includes bipolar transistor 12b and MOS transistor 14b connected in series, with the gate of MOS transistor 14b receiving input voltage V.sub.i-. The sources of MOS transistors 14a, 14b (and their body nodes) are connected together at common node CN.
The reference leg of transconductance stage 10 includes current source 15, which conducts current I.sub.D from power supply voltage V.sub.dd. Bipolar transistor 16 has its collector and base connected to current source 15, and connected to the bases of transistors 12a, 12b in the differential legs. The emitter of bipolar transistor 16 is connected to resistor 18, which is connected on its other side to common node CN. Current source 19 conducts current I.sub.SUM (i.e., the sum of currents I.sub.D, I.sub.0+, I.sub.0-) between common node CN and ground.
In transconductance stage 10, each of MOS transistors 14a, 14b os to be biased in its triode region (i.e., V.sub.ds &lt;V.sub.gs -V.sub.th, where V.sub.th is the MOS threshold voltage of transistors 14a, 14b), so that its drain-source current (I.sub.ds) is linearly proportional to its gate-source voltage (V.sub.gs), so long as its drain-source voltage (V.sub.ds) remains constant. The current I.sub.D conducted by resistor 18 establishes the drain-source voltages for transistors 14a, 14b. Bipolar transistors 12a, 12b, (biased by transistor 16) minimize variations in the potential at the drains of transistors 14a, 14b, since their base-emitter voltages are substantially constant over variations in their collector current (I.sub.0+, I.sub.0-, respectively). Accordingly, one may calculate the differential output current .DELTA.I.sub.0 (the difference between I.sub.0+ and I.sub.0-) as follows: ##EQU1## or, since k.sub.N =.mu.C.sub.ox (W/L), ##EQU2## where .mu. is the mobility, C.sub.ox is the gate oxide capacitance, and W/L is the channel width-to-length ratio of transistors 14, assuming matched construction. Accordingly, the differential current .DELTA.I.sub.0 is a linear function of the differential input voltage V.sub.i+ -V.sub.i-,
As described in the above-incorporated U.S. Pat. No. 5,332,937, a transconductance stage such as transconductance stage 10 of FIG. 1 has been utilized in a continuous-time filter, and has been observed to provide highly linear behavior and good frequency performance.
It is an object of the present invention to provide a high frequency analog multiplier that has a large input dynamic range.
It is a further object of the present invention to provide such a multiplier circuit which is operable at low power supply voltages, as useful in low power telecommunication and portable computing applications.
It is a further object of the present invention to provide such a multiplier circuit which has relatively low power dissipation for its frequency performance, as useful in low power telecommunication and portable computing applications.
It is a further object of the present invention to provide such a multiplier circuit that has very low total harmonic distortion.
It is a further object of the present invention to provide such a multiplier circuit that may be implemented with a small number of transistors.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.